AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 151

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

6-4
3
2
1
RES
EADISEL
AWAKE
ASEL
Reserved locations. Written as
zeros and read as undefined.
EADI Select. When set to 1, this
bit enables the three EADI inter-
face pins that are multiplexed
with other functions. EESK/LED1
becomes SFBD, EEDO/LED3
becomes SRD, LED2 becomes
SRDCLK, and SLEEP becomes
EAR. See the section on External
Address Detection for more de-
tails.
This bit selects one of two differ-
ent sleep modes.
Auto Select. When set, the
Am79C971 controller will auto-
matically select the operating me-
interrupt channels to be shared
by multiple devices.
INTLEVEL should not be set to 1
when the Am79C971 controller is
used in a PCI bus application.
Read/Write accessible always.
INTLEVEL is cleared to 0 by
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
Read/Write accessible always.
EADISEL
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
If AWAKE is set to 1 and the
SLEEP pin is asserted, the
Am79C971 controller goes into
snooze mode. If AWAKE is
cleared to 0 and the SLEEP pin is
asserted, the Am79C971 control-
ler goes into coma mode. See the
section Power Saving Modes for
more details.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/Write accessible always.
AWAKE is cleared to 0 by
H_RESET and is unaffected by
S_RESET or by setting the STOP
bit.
is
cleared
P R E L I M I N A R Y
Am79C971
by
0
XMAUSEL
dia interface port. If ASEL has
been set to a 1, then when the MI-
IPD bit (BCR32, bit 14) is 1, the
MII port is selected. If the MIIPD
bit is 0, and then, if the 10BASE-
T transceiver is in the link pass
state (due to receiving valid frame
data and/or Link Test pulses or
the DLNKTST bit is set), the
10BASE-T port will be used. If the
MIIPD bit is 0 and the 10BASE-T
port is in the Link Fail state, the
AUI port will be used. Switching
between the ports will not occur
during transmission to avoid any
type of fragment generation.
The network port configurations
are found in Table 31.
When ASEL is set to 1 and the
MIIPD bit is 0, Link Beat Pulses
will
10BASE-T port, regardless of the
state of Link Status. When ASEL
is reset to 0, Link Beat Pulses will
only
10BASE-T port when the PORT-
SEL bits of the Mode Register
(CSR15) have selected 10BASE-
T as the active port.
When ASEL is set to a 0, then the
selected network port will be de-
termined by the settings of the
PORTSEL bits of CSR15. When
ASEL is set to 1, the selected net-
work port may be determined
through software by reading the
MIIPD bit and, if MIIPD is 0, read-
ing the link status through BCR4
or another LED Control register if
it is programmed for link status.
The PORTSEL[1:0] bits do not
reflect the selected network port
when ASEL is 1. Read/Write ac-
cessible always. ASEL is set to 1
by H_RESET and is unaffected
by S_RESET or STOP.
Reserved location. Read/Write
accessible always. This reserved
location is cleared by H_RESET
and is unaffected by S_RESET or
STOP. Writing a 1 to this bit has
no effect on the operation of the
Am79C971 controller.
be
be
transmitted
transmitted
on
on
151
the
the