AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 76

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

The MAC engine changes for full-duplex operation are
as follows:
The T-MAU changes for full-duplex operation are as fol-
lows:
The MII changes for full-duplex operation are as fol-
lows:
Full-Duplex Link Status LED Support
The Am79C971 controller provides bits in each of the
LED Status registers (BCR4, BCR5, BCR6, BCR7) to
display the Full-Duplex Link Status. If the FDLSE bit
(bit 8) is set, a value of 1 will be sent to the associated
76
transmitted, the XMTFW bits (CSR80, bits 9-8) al-
ways govern when transmit DMA is requested.
Successful reception of the first 64 bytes of every
receive frame is not a requirement for Receive DMA
to begin as described in the Receive Exception
Conditions section. Instead, receive DMA will be re-
quested as soon as either the RCVFW threshold
(CSR80, bits 12-13) is reached or a complete valid
receive frame is detected, regardless of length. This
Receive FIFO operation is identical to when the
RPA bit (CSR124, bit 3) is set during half-duplex
mode operation.
Changes to the Transmit Deferral mechanism:
— Transmission is not deferred while receive is
— The IPG counter which governs transmit deferral
When the AUI or MII port is active, Loss of Carrier
(LCAR) reporting is disabled (LCAR is still reported
when the 10BASE-T port is active if a packet is
transmitted while in Link Fail state).
The 4.0
transmission during which the SQE test normally
occurs is disabled.
When the AUI port is active, the SQE Test error re-
porting (CERR) is disabled (CERR is still reported
when the 10BASE-T port is active if a packet is
transmitted while in Link Fail state).
The collision indication input to the MAC engine is
ignored.
The transmit to receive loopback path in the T-MAU
is disabled.
The collision detect circuit is disabled.
The SQE test function is disabled.
The collision detect (COL) pin is disabled.
The SQE test function is disabled.
active.
during the IPG between back-to-back transmits
is started when transmit activity for the first
packet ends, instead of when transmit and car-
rier activity ends.
s carrier sense blinding period after a
Am79C971
LEDOUT bit when the T-MAU is in the Full-Duplex
Link Pass state only.
Media Independent Interface
The Am79C971 controller fully supports the MII ac-
cording to the IEEE 802.3 standard. This Reconcilia-
tion Sublayer interface allows a variety of PHYs
( 1 0 0 B A S E - T X , 1 0 0 B A S E - F X , 1 0 0 B A S E - T 4 ,
100BASE-T2, 10BASE-T, etc.) to be attached to the
Am79C971 MAC engine without future upgrade prob-
lems. The MII interface is a 4-bit (nibble) wide data path
interface that runs at 25 MHz for 100-Mbps networks
and 2.5 MHz for 10-Mbps networks. The interface con-
s is ts of t wo i nd ep end ent dat a pa ths, r ec ei ve
(RXD(3:0)) and transmit (TXD(3:0)), control signals for
each data path (RX_ER, RX_DV, TX_ER, TX_EN), net-
work status signals (COL, CRS), clocks (RX_CLK,
TX_CLK) for each data path, and a two-wire manage-
ment interface (MDC and MDIO). See Figure 38.
MII Transmit Interface
The MII transmit clock is generated by the external
PHY and is sent to the Am79C971 controller on the
TX_CLK input pin. The clock can run at 25 MHz or 2.5
MHz, depending on the speed of the network that the
external PHY is attached to. The data is a nibble-wide
(4 bits) data path, TXD(3:0), from the Am79C971 con-
troller to the external PHY and is synchronous to the
rising edge of TX_CLK. The transmit process starts
when the Am79C971 controller asserts the TX_EN,
which indicates to the external PHY that the data on
TXD(3:0) is valid.
Normally, unrecoverable errors are signaled through
the MII to the external PHY with the TX_ER output pin.
The external PHY will respond to this error by generat-
ing a TX coding error on the current transmitted frame.
The Am79C971 controller does not use this method of
signaling errors on the transmit side. The Am79C971
controller will invert the FCS on the last byte generating
an invalid FCS. The TX_ER pin is reserved for future
use and is actively driven to 0.
MII Receive Interface
The MII receive clock is also generated by the external
PHY and is sent to the Am79C971 controller on the
RX_CLK input pin. The clock will be the same fre-
quency as the TX_CLK but will be out of phase and can
run at 25 MHz or 2.5 MHz, depending on the speed of
the network the external PHY is attached to. The
RX_CLK is a continuous clock during the reception of
the frame, but can be stopped for up to two RX_CLK
periods at the beginning and the end of frames, so that
the external PHY can sync up to the network data traffic
necessary to recover the receive clock. During this
time, the external PHY may switch to the TX_CLK to
maintain a stable clock on the receive interface. The
Am79C971 controller will handle this situation with no
loss of data. The data is a nibble-wide (4 bits) data