AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 103

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

I/O Resources
The Am79C971 controller requires 32 bytes of address
space for access to all the various internal registers as
well as to some setup information stored in an external
serial EEPROM. A software reset port is available, too.
The Am79C971 controller supports mapping the ad-
dress space to both I/O and memory space. The value
in the PCI I/O Base Address register determines the
start address of the I/O address space. The register is
typically programmed by the PCI configuration utility
after system power-up. The PCI configuration utility
must also set the IOEN bit in the PCI Command regis-
ter to enable I/O accesses to the Am79C971 controller.
For memory mapped I/O access, the PCI Memory
Mapped I/O Base Address register controls the start
address of the memory space. The MEMEN bit in the
PCI Command register must also be set to enable the
mode. Both base address registers can be active at the
same time.
The Am79C971 controller supports two modes for ac-
cessing the I/O resources. For backwards compatibility
with AMD’s 16-bit Ethernet controllers, Word I/O is the
default mode after power up. The device can be config-
ured to DWord I/O mode by software.
I/O Registers
The Am79C971 controller registers are divided into two
groups. The Control and Status Registers (CSR) are
used to configure the Ethernet MAC engine and to ob-
tain status information. The Bus Control Registers
31
Base-Class
MAX_LAT
Reserved
24
Subsystem ID
Device ID
Status
23
Header Type
Sub-Class
MIN_GNT
Memory Mapped I/O Base Address
Expansion ROM Base Address
Table 19.
I/O Base Address
16
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PCI Configuration Space Layout
15
Am79C971
Programming IF
Latency Timer
Interrupt Pin
(BCR) are used to configure the bus interface unit and
the LEDs. Both sets of registers are accessed using in-
direct addressing.
The CSR and BCR share a common Register Address
Port (RAP). There are, however, separate data ports.
The Register Data Port (RDP) is used to access a
CSR. The BCR Data Port (BDP) is used to access a
BCR.
In order to access a particular CSR location, the RAP
should first be written with the appropriate CSR ad-
dress. The RDP will then point to the selected CSR. A
read of the RDP will yield the selected CSR data. A
write to the RDP will write to the selected CSR. In order
to access a particular BCR location, the RAP should
first be written with the appropriate BCR address. The
BDP will then point to the selected BCR. A read of the
BDP will yield the selected BCR data. A write to the
BDP will write to the selected BCR.
Once the RAP has been written with a value, the RAP
value remains unchanged until another RAP write oc-
curs, or until an H_RESET or S_RESET occurs. RAP
is cleared to all 0s when an H_RESET or S_RESET oc-
curs. RAP is unaffected by setting the STOP bit.
Address PROM Space
The Am79C971 controller allows for connection of a
serial EEPROM. The first 16 bytes of the EEPROM will
be automatically loaded into the Address PROM
(APROM) space after H_RESET. The Address PROM
space is a convenient place to store the value of the 48-
Subsystem Vendor ID
8
Command
Vendor ID
7
Interrupt Line
Revision ID
Reserved
0
Offset
0Ch
1Ch
2Ch
3Ch
FCh
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
.
.
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