AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 260

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

Bus Master DMA Transfers
C
Carrier Tracking and End of Message
Clock Acquisition
Collision Detection
Collision Handling
Compatible (with Am79C971 device)
Control and Status Registers
I-2
BCR6
BCR7
BCR9
10BASE-T Filters and Transformers
AUI Isolation Transformers
DC/DC Converters
Media Interface Modules
CSR0
CSR1
CSR10
CSR100
CSR11
CSR112
CSR114
CSR12
CSR122
CSR124
CSR125
CSR13
CSR14
CSR15
CSR16
CSR17
CSR18
CSR19
CSR2
LED2 Status
LED3 Status
Full-Duplex Control
Am79C971 Controller Status and
Initialization Block Address 0
Logical Address Filter 2
Bus Timeout
Logical Address Filter 3
Missed Frame Count
Receive Collision Count
Physical Address Register 0
Advanced Feature Control
Test Register 1
MAC Enhanced Configuration Control
Physical Address Register 1
Physical Address Register 2
Mode
Initialization Block Address Lower
Initialization Block Address Upper
Current Receive Buffer Address Lower 133
Current Receive Buffer Address Upper 133
Control Register
115–148
157
160
163
115
118
129
146
129
147
147
129
147
147
147
130
130
130
133
133
A-1
A-2
A-2
A-1
37
71
71
72
63
CSR20
CSR21
CSR22
CSR23
CSR24
CSR25
CSR26
CSR27
CSR28
CSR29
CSR3
CSR30
CSR31
CSR32
CSR33
CSR34
CSR35
CSR36
CSR37
CSR38
CSR39
CSR4
CSR40
CSR41
CSR42
Initialization Block Address 1
Current Transmit Buffer Address Lower 133
Current Transmit Buffer Address Upper 133
Next Receive Buffer Address Lower
Next Receive Buffer Address Upper
Base Address of Receive Ring Lower
Base Address of Receive Ring Upper
Next Receive Descriptor Address Lower134
Next Receive Descriptor Address Upper134
Current Receive Descriptor Address
Current Receive Descriptor Address
Interrupt Masks and Deferral Control
Base Address of Transmit Ring Lower 135
Base Address of Transmit Ring Upper 135
Next Transmit Descriptor Address Lower135
Next Transmit Descriptor Address Upper135
Current Transmit Descriptor Address Lower
Current Transmit Descriptor Address
Next Next Receive Descriptor Address
Next Next Receive Descriptor Address
Next Next Transmit Descriptor Address Lower
Next Next Transmit Descriptor Address Upper
Test and Features Control
Current Receive Byte Count
Current Receive Status
Lower
Upper
Upper
118
134
134
134
134
134
135
118
135
135
136
136
136
136
121
136
136