AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 132

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

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4
3
132
PORTSEL [1:0]
XX
XX
XX
00
01
10
11
DRTY
FCOLL
DXMTFCS Disable Transmit CRC (FCS).
ASEL
(BCR2[1])
1
1
1
0
0
0
0
to 1, the Am79C971 controller will
attempt only one transmission. In
this mode, the device will not pro-
tect the first 64 bytes of frame
data in the Transmit FIFO from
being overwritten, because auto-
matic retransmission will not be
necessary. When DRTY is set to
0, the Am79C971 controller will
attempt 16 transmissions before
signaling a retry error.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
the collision logic to be tested.
The Am79C971 controller must
be in internal loopback for FCOLL
to be valid. If FCOLL = 1, a colli-
sion will be forced during loop-
back
which will result in a Retry Error.
If FCOLL = 0, the Force Collision
logic will be disabled. FCOLL is
defined after the initialization
block is read.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
When DXMTFCS is set to 0, the
transmitter will generate and ap-
pend an FCS to the transmitted
frame. When DXMTFCS is set to
1, no FCS is generated or sent
with
DXMTFCS is overridden when
ADD_FCS is set in TMD1.
11) is set to 1, the setting of
Disable Retry. When DRTY is set
Force Collision. This bit allows
When APAD_XMT (CSR4, bit
the
transmission
transmitted
Table 26. Network Port Configuration.
Link Status
(10BASE-T)
Fail
Pass
Don’t Care
Don’t Care
Don’t Care
Don’t Care
Don’t Care
attempts,
frame.
Am79C971
2
LOOP INTL
Table 27. Loopback Configuration for AUI
0
1
1
1
MII Status
(BCR32[14])
0
0
1
Don’t Care
Don’t Care
Don’t Care
Don’t Care
LOOP
X
0
1
1
MENDECL
X
X
0
1
If
ADD_FCS is clear for a particular
frame, no FCS will be generated.
The value of ADD_FCS is valid
only when STP is set in TMD1. If
ADD_FCS is set for a particular
frame, the state of DXMTFCS is
ignored and a FCS will be ap-
pended on that frame by the
transmit circuitry. See also the
ADD_FCS bit in TMD1.
This bit was called DTCR in the
LANCE (Am7990) device.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
DXMTFCS has no effect on
frames shorter than 64 bytes.
Am79C971 controller to operate
in full-duplex mode for test pur-
poses. The setting of the full-
duplex control bits in BCR9 have
no effect when the device oper-
ates in loopback mode. When
LOOP = 1, loopback is enabled.
In combination with INTL and
MENDECL,
modes are defined as follows in
Table 27. Refer to Loop Back Op-
eration section for more details.
Loopback Enable allows the
DXMTFCS
Loopback Mode
Non-loopback
External Loopback
Internal Loopback Include
MENDEC
Internal Loopback
Exclude MENDEC
Network
Port
AUI
10BASE-T
MII
AUI
10BASE-T
GPSI
MII
various
is
set
loopback
and