AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 39

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

Basic Non-Burst Write Transfer
By default, the Am79C971 controller uses non-burst
cy cles i n a ll bus ma ster wr ite operations. All
Am79C971 controller non-burst write accesses are of
the PCI command type Memory Write (type 7). The
byte enable signals indicate the byte lanes that have
valid data.The Am79C971 controller typically performs
more than one non-burst write transaction within a sin-
gle bus mastership period. FRAME is dropped be-
tween consecutive non-burst write cycles. REQ,
however, stays asserted until FRAME is asserted for
the last transaction. The Am79C971 supports zero wait
state write cycles except with descriptor write transfers.
(See the section Descriptor DMA Transfers for the only
exception.) It asserts IRDY immediately after the ad-
dress phase.
Figure 14 shows two non-burst write transactions. The
first transaction has two wait states. The target inserts
one wait state by asserting DEVSEL one clock late and
another wait state by also asserting TRDY one clock
late. The second transaction shows a zero wait state
write cycle. The target asserts DEVSEL and TRDY in
the same cycle as the Am79C971 controller asserts
IRDY.
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
PAR
CLK
AD
1
DEVSEL is sampled
Figure 14. Non-Burst Write Transfer
2
ADDR
0111
3
PAR
Am79C971
4
DATA
BE
5
Basic Burst Write Transfer
The Am79C971 controller supports burst mode for all
bus master write operations. The burst mode must be
enabled by setting BWRITE (BCR18, bit 5). To allow
burst transfers in descriptor write operations, the
Am79C971 controller must also be programmed to use
SWSTYLE 3 (BCR20, bits 7-0). All Am79C971 control-
ler burst write transfers are of the PCI command type
Memory Write (type 7). AD[1:0] will both be 0 during the
address phase indicating a linear burst order. The byte
enable signals indicate the byte lanes that have valid
data.
The Am79C971 controller will always perform a single
burst write transaction per bus mastership period,
where transaction is defined as one address phase and
one or multiple data phases. The Am79C971 controller
supports zero wait state write cycles except with the
case of descriptor write transfers. (See the section De-
scriptor DMA Transfers for the only exception.) The de-
vice asserts IRDY immediately after the address phase
and at the same time star ts sampling DEVSEL.
FRAME is deasserted when the next to last data phase
is completed.
PAR
6
7
ADDR
0111
8
DATA
PAR
BE
9
PAR
10
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