AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 171

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

7-0
BCR22: PCI Latency Register
Note: Bits 15-0 in this register are programmable
through the EEPROM.
Bit
31-16 RES
15-8
SWSTYLE
MAX_LAT
Name
SWSTYLE
All Other
[7:0]
00h
01h
02h
03h
Software Style register. The val-
ue in this register determines the
style of register and memory re-
sources that shall be used by the
Am79C971 controller. The Soft-
ware Style selection will affect the
interpretation of a few bits within
the CSR space, the order of the
descriptor entries and the width of
the descriptors and initialization
block entries.
Reserved locations. Written as
zeros and read as undefined.
Maximum Latency. Specifies the
maximum arbitration latency the
Am79C971 controller can sustain
without causing problems to the
network activity. The register val-
ue specifies the time in units of 1/
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address bits. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit
(BCR18, bit 7).
Description
PCnet-ISA
PCnet-PCI
PCnet-PCI
Reserved
controller
controller
controller
LANCE/
Name
Style
RES
Table 36. Software Styles
P R E L I M I N A R Y
Undefined
Am79C971
SSIZE32
0
1
1
1
BCR21: Interrupt Control
Bit
31-16 RES
15-0
16-bit software
structures, non-burst or
burst access
RES
32-bit software
structures, non-burst or
burst access
32-bit software
structures, non-burst or
burst access
Undefined
INTCON
Name
Initialization Block
Entries
All Am79C971 controller CSR
bits and all descriptor, buffer, and
initialization block entries not cit-
ed in the Table 36 are unaffected
by the Software Style selection
and are, therefore, always fully
functional as specified in the CSR
and BCR sections.
Read/Write accessible only when
either the STOP or the SPND bit
is set. The SWSTYLE register will
contain the value 00h following
H_RESET and will be unaffected
by S_RESET or STOP.
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Writes to this
register will have no effect on the
operation of the Am79C971 con-
troller.
4 microseconds. MAX_LAT is
aliased to the PCI configuration
space register MAX_LAT (offset
3Fh). The host will use the value
in the register to determine the
setting of the Am79C971 Latency
Timer register.
Read accessible always; write
accessible only when either the
STOP or the SPND bit is set.
MAX_LAT is set to the value of
FFh by H_RESET which results
in a default maximum latency of
63.75 microseconds. It is recom-
Description
16-bit software structures,
non-burst access only
RES
32-bit software structures,
non-burst access only
32-bit software structures,
non-burst access only
Undefined
Descriptor Ring Entries
171