AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 234

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

The most critical pins in the layout of a Am79C971 de-
sign are the four analog power and two analog ground
pins, VDD_PLL, AVDD, VSS_PLL and AVSS respec-
tively. All of these pins are located in one corner of the
device, the “analog corner.” Specific functions and lay-
out requirements of the analog power and ground pins
are given below.
AVSS and AVDD
These pins provide the power and ground for the
Twisted Pair and AUI drivers. In addition AVSS serves
as the ground for the logic interfaces in the 20 MHz
Crystal Oscillator. Hence, these pins can be very noisy.
To determine the value for the resistor and capacitor,
the formula is:
R * C
where R is in Ohms and C is in microfarads. Some pos-
sible combinations are given below. To minimize the
voltage drop across the resistor, the R value should not
be more than 10 .
Note: The capacitor used should be tantalum not alu-
minum electrolytic.5.0
VSS_PLL and VDD_PLL/AVDD
These pins provide power and ground for the AUI and
twisted pair receive circuitry. In addition, as mentioned
earlier, VSS_PLL and VDD_PLL provide power and
ground for the phase-lock loop portion of the chip. Ex-
B-2
88
2.7
4.3
6.8
10
R
Figure 2. Power and Ground Pin Connections
VDD Plane
Am79C971
VDD_PLL
(Pin 129)
33 F
22 F
15 F
10 F
C
VSS_PLL
Am79C971
(Pin 119)
A dedicated 0.1 F capacitor between these pins is
recommended.
VSS_PLL and VDD_PLL
These pins are the most critical pins on the
Am79C971 device because they provide the power
and ground for the phase-lock loop (PLL) portion of the
chip. The voltage-controlled oscillator (VCO) portion of
the PLL is sensitive to noise in the 60 kHz - 200 kHz.
range. To prevent noise in this frequency range from
disrupting the VCO, it is strongly recommended that
the low-pass filter shown below be implemented on
these pins when internal ports are used.This filter is not
needed when MII is used solely.
cept for the filter circuit already mentioned, no specific
decoupling is necessary on these pins.
AVDD
AVDD provides power for the control and interface logic
in the PLL. Ground for this logic is provided by digital
ground pins. No specific decoupling is necessary on
this pin.
Special Note for Adapter Cards: In adapter card de-
signs, it is important to utilize all available power
and ground pins available on the bus edge connec-
tor. In addition, the connection from the bus edge con-
nector to the power or ground plane should be made
through more than one via and with wide traces (15
mils desirable) wherever possible. Following these rec-
ommendations results in minimal inductance in the
power and ground paths. By minimizing this induc-
tance, ground bounce is minimized.
See also the PCnet™ Family Board Design and Layout
Recommendations applications note (PID# 19595) for
additional information.
33 F to 10 F
0.1 F
1
2.7
to 10
VSS Plane
19364D-2