AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 142

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

CSR72: Receive Ring Counter
Bit
31-16 RES
15-0
CSR74: Transmit Ring Counter
Bit
31-16 RES
15-0
CSR76: Receive Ring Length
Bit
31-16 RES
15-0
142
RCVRC
XMTRC
RCVRL
Name
Name
Name
Reserved locations. Written as
zeros and read as undefined.
Receive Ring Counter location.
Contains a two’s complement bi-
nary number used to number the
current receive descriptor. This
counter interprets the value in
CSR76 as pointing to the first de-
scriptor. A counter value of zero
corresponds to the last descriptor
in the ring.
Reserved locations. Written as
zeros and read as undefined.
Transmit Ring Counter location.
Contains a two’s complement bi-
nary number used to number the
current transmit descriptor. This
counter interprets the value in
CSR78 as pointing to the first de-
scriptor. A counter value of zero
corresponds to the last descriptor
in the ring.
Reserved locations. Written as
zeros and read as undefined.
Receive Ring Length. Contains
the two’s complement of the re-
ceive descriptor ring length. This
register is initialized during the
Am79C971 controller initializa-
tion routine based on the value in
the RLEN field of the initialization
block. However, this register can
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
Description
Description
P R E L I M I N A R Y
Am79C971
CSR78: Transmit Ring Length
Bit
31-16 RES
15-0
CSR80: DMA Transfer Counter and FIFO Threshold
Control
Bit
31-16 RES
15-14 RES
13-12 RCVFW[1:0] Receive
XMTRL
Name
Name
be manually altered. The actual
receive ring length is defined by
the current value in this register.
The ring length can be defined as
any value from 1 to 65535.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the Am79C971 controller initial-
ization routine based on the value
in the TLEN field of the initializa-
tion block. However, this register
can be manually altered. The ac-
tual transmit ring length is defined
by the current value in this regis-
ter. The ring length can be de-
fined as any value from 1 to
65535.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
RCVFW controls the point at
which receive DMA is requested
in relation to the number of re-
ceived bytes in the Receive FIFO.
RCVFW specifies the number of
bytes which must be present
(once the frame has been verified
as a non-runt) before receive
Description
Description
FIFO
Watermark.