AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 133

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

1
0
CSR16: Initialization Block Address Lower
Bit
31-16
15-0
CSR17: Initialization Block Address Upper
Bit
31-16
15-0
DTX
DRX
Name
RES
IADRL
Name
RES
IADRH
Read/Write accessible only when
either the STOP or the SPND bit
is set. LOOP is cleared by
H_RESET or S_RESET and is
unaffected by STOP.
Am79C971 controller not access-
ing the Transmit Descriptor Ring
and, therefore, no transmissions
are attempted. DTX = 0, will set
TXON bit (CSR0 bit 4) if STRT
(CSR0 bit 1) is asserted.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Am79C971 controller not access-
ing the Receive Descriptor Ring
and, therefore, all receive frame
data are ignored. DRX = 0, will
set RXON bit (CSR0 bit 5) if
STRT (CSR0 bit 1) is asserted.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
zeros and read as undefined.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
zeros and read as undefined.
Read/Write accessible only when
either the STOP or the SPND bit
is set.
Disable
Disable Receiver results in the
Description
Reserved locations. Written as
This register is an alias of CSR1.
Description
Reserved locations. Written as
This register is an alias of CSR2.
Transmit
results
Am79C971
in
CSR18: Current Receive Buffer Address Lower
Bit
31-16 RES
15-0
CSR19: Current Receive Buffer Address Upper
Bit
31-16 RES
15-0
CSR20: Current Transmit Buffer Address Lower
Bit
31-16 RES
15-0
CSR21: Current Transmit Buffer Address Upper
Bit
31-16 RES
Name
CRBAL
Name
CRBAU
Name
CXBAL
Name
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
zeros and read as undefined.
current receive buffer address at
which the Am79C971 controller
will store incoming frame data.
Description
zeros and read as undefined.
current receive buffer address at
which the Am79C971 controller
will store incoming frame data.
Description
zeros and read as undefined.
current transmit buffer address
from which the Am79C971 con-
troller is transmitting.
Description
zeros and read as undefined.
Reserved locations. Written as
Contains the lower 16 bits of the
Reserved locations. Written as
Contains the upper 16 bits of the
Reserved locations. Written as
Contains the lower 16 bits of the
Reserved locations. Written as
133