AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 114

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

PCI Interrupt Line Register
Offset 3Ch
The PCI Interrupt Line register is an 8-bit register that
is used to communicate the routing of the interrupt.
This register is written by the POST software as it ini-
tializes the Am79C971 controller in the system. The
register is read by the network driver to determine the
interrupt channel which the POST software has as-
signed to the Am79C971 controller. The PCI Interrupt
Line register is not modified by the Am79C971 control-
ler. It has no effect on the operation of the device.
The PCI Interrupt Line register is located at offset 3Ch
in the PCI Configuration Space. It is read and written by
the host. It is cleared by H_RESET and is not affected
S_RESET or by setting the STOP bit.
PCI Interrupt Pin Register
Offset 3Dh
This PCI Interrupt Pin register is an 8-bit register that
indicates the interrupt pin that the Am79C971 controller
is using. The value for the Am79C971 Interrupt Pin reg-
ister is 01h, which corresponds to INTA.
The PCI Interrupt Pin register is located at offset 3Dh
in the PCI Configuration Space. It is read only.
PCI MIN_GNT Register
Offset 3Eh
The PCI MIN_GNT register is an 8-bit register that
specifies the minimum length of a burst period that the
Am79C971 needs to keep up with the network activity.
The length of the burst period is calculated assuming a
clock rate of 33 MHz. The register value specifies the
time in units of 1/4 s. The PCI MIN_GNT register is an
alias of BCR22, bits 7-0. The default value for
MIN_GNT is 06h, which corresponds to a minimum
grant of 1.5
Am79C971 controller to read/write half of the FIFO. (16
DWord transfers in burst mode with one extra wait state
per data phase inserted by the target.) Note that the
default is only a typical value. This calculation also
does not take into account any descriptor accesses.
The host should use the value in this register to deter-
mine the setting of the PCI Latency Timer register.
The PCI MIN_GNT register is located at offset 3Eh in
the PCI Configuration Space. It is read only.
114
s and which is the time it takes the
ROMEN is read and written by
the host. ROMEN is cleared by
H_RESET and is not effected by
S_RESET or by setting the STOP
bit.
Am79C971
PCI MAX_LAT Register
Offset 3Fh
The PCI MAX_LAT register is an 8-bit register that
specifies the maximum arbitration latency the
Am79C971 controller can sustain without causing
problems to the network activity. The register value
specifies the time in units of 1/4 s. The MAX_LAT reg-
ister is an alias of BCR22, bits 15-8. It is recommended
that BCR22 be programmed to the value of 1818H.
The host should use the value in this register to deter-
mine the setting of the PCI Latency Timer register.
The PCI MAX_LAT register is located at offset 3Fh in
the PCI Configuration Space. It is read only.
RAP Register
The RAP (Register Address Pointer) register is used to
gain access to CSR and BCR registers on board the
Am79C971 controller. The RAP contains the address
of a CSR or BCR.
As an example of RAP use, consider a read access to
CSR4. In order to access this register, it is necessary
to first load the value 0004h into the RAP by performing
a write access to the RAP offset of 12h (12h when WIO
mode has been selected, 14h when DWIO mode has
been selected). Then a second access is performed,
this time to the RDP offset of 10h (for either WIO or
DWIO mode). The RDP access is a read access, and
since RAP has just been loaded with the value of
0004h, the RDP read will yield the contents of CSR4. A
read of the BDP at this time (offset of 16h when WIO
mode has been selected, 1Ch when DWIO mode has
been selected) will yield the contents of BCR4, since
the RAP is used as the pointer into both BDP and RDP
space.
RAP: Register Address Port
Bit
31-16 RES
15-8
7-0
Name
RES
RAP
A write access to undefined CSR
or BCR locations may cause un-
expected reprogramming of the
Am79C971 control registers. A
Description
zeros and read as undefined.
written as zeros.
of these 8 bits determines which
CSR or BCR will be accessed
when an I/O access to the RDP
or BDP port, respectively, is per-
formed.
Reserved locations. Written as
Reserved locations. Read and
Register Address Port. The value