AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 134

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

15-0
CSR22: Next Receive Buffer Address Lower
Bit
31-16
15-0
CSR23: Next Receive Buffer Address Upper
Bit
31-16
15-0
CSR24: Base Address of Receive Ring Lower
Bit
31-16
15-0
134
CXBAU
Name
Name
RES
NRBAU
Name
RES
BADRL
NRBAL
RES
current transmit buffer address
from which the Am79C971 con-
troller is transmitting.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
next receive buffer address to
which the Am79C971 controller
will store incoming frame data.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
next receive buffer address to
which the Am79C971 controller
will store incoming frame data.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
base address of the Receive
Ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
Contains the upper 16 bits of the
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
Description
Reserved locations. Written as
Contains the upper 16 bits of the
Description
Reserved locations. Written as
Contains the lower 16 bits of the
Am79C971
CSR25: Base Address of Receive Ring Upper
Bit
31-16 RES
15-0
CSR26: Next Receive Descriptor Address Lower
Bit
31-16 RES
15-0
CSR27: Next Receive Descriptor Address Upper
Bit
31-16 RES
15-0
CSR28: Current Receive Descriptor Address Lower
Bit
31-16 RES
Name
BADRU
Name
NRDAL
Name
NRDAU
Name
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Description
zeros and read as undefined.
Contains the upper 16 bits of the
base address of the Receive
Ring.
Description
zeros and read as undefined.
Contains the lower 16 bits of the
next receive descriptor address
pointer.
Description
zeros and read as undefined.
Contains the upper 16 bits of the
next receive descriptor address
pointer.
Description
zeros and read as undefined.
Reserved locations. Written as
Reserved locations. Written as
Reserved locations. Written as
Reserved locations. Written as