AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 170

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

BCR20: Software Style
This register is an alias of the location CSR58. Accesses
to and from this register are equivalent to accesses to
CSR58.
Bit
31-16 RES
15-11 RES
10
9
8
170
RST Pin
High
High
High
Low
APERREN
RES
SSIZE32
Name
Read in Progress
PREAD or Auto
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
Advanced Parity Error Handling
Enable. When APERREN is set
to 1, the BPE bits (RMD1 and
TMD1, bit 23) start having a
meaning. BPE will be set in the
descriptor associated with the
buffer that was accessed when a
data parity error occurred. Note
that since the advanced parity er-
ror handling uses an additional bit
in the descriptor, SWSTYLE (bits
7-0 of this register) must be set to
2 or 3 to program the Am79C971
controller to use 32-bit software
structures.
Reserved locations. Written as
zeros; read as undefined.
Software Size 32 bits. When set,
this
Am79C971 controller utilizes 32-
bit software structures for the ini-
tialization block and the transmit
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur when
the Am79C971 controller is the
target of the transfer.
Read anytime; write accessible
only when either the STOP or the
SPND bit is set. APERREN is
cleared by H_RESET and is not
affected by S_RESET or STOP.
Description
X
1
0
0
bit
indicates
Table 35. Interface Pin Assignment
EEN
X
X
1
0
P R E L I M I N A R Y
that
the
Am79C971
Bit of BCR19
From ECS
EECS
Active
0
0
From ESK Bit of
Tri-State
BCR19
EESK
Active
LED1
and receive descriptor entries.
When cleared, this bit indicates
that the Am79C971 controller uti-
lizes 16-bit software structures for
the initialization block and the
transmit and receive descriptor
entries.
Am79C971 controller is back-
wards
Am7990 LANCE and Am79C960
PCnet-ISA controllers.
The value of SSIZE32 is deter-
mined by the Am79C971 control-
ler according to the setting of the
Software Style (SWSTYLE, bits
7-0 of this register).
Read
SSIZE32 is read only; write oper-
ations will be ignored. SSIZE32
will be cleared after H_RESET
(since SWSTYLE defaults to 0)
and is not affected by S_RESET
or STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32-bit address
bus during master accesses initi-
ated by the Am79C971 controller.
This action is required, since the
16-bit software structures speci-
fied by the SSIZE32 = 0 setting
will yield only 24 bits of address
for Am79C971 controller bus
master accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the Am79C971 controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the Am79C971
controller for performing master
accesses.
compatible
In
accessible
this
From EEDI Bit of
Tri-State
BCR19
Active
LED0
EEDI
mode,
with
always.
the
the