AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 147

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

CSR112: Missed Frame Count
Bit
31-16 RES
15-0
CSR114: Receive Collision Count
Bit
31-16 RES
15-0
CSR122: Advanced Feature Control
Bit
31-16 RES
15-1
MFC
RCC
RES
Name
Name
Name
Reserved locations. Written as
zeros and read as undefined.
Missed Frame Count. Indicates
the number of missed frames.
Reserved locations. Written as
zeros and read as undefined.
Receive Collision Count. Indi-
cates the total number of colli-
sions
receiver since the last reset of the
counter.
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
Read/Write accessible only when
either the STOP or the SPND bit
is set. This register is set to
0600h
S_RESET and is unaffected by
STOP.
MFC will roll over to a count of 0
from the value 65535. The MFCO
bit of CSR4 (bit 8) will be set each
time that this occurs.
Read accessible always. MFC is
read only, write operations are ig-
nored.
H_RESET or S_RESET or by
setting the STOP bit.
RCC will roll over to a count of 0
from the value 65535. The
RCVCCO bit of CSR4 (bit 5) will
be set each time that this occurs.
Read accessible always. RCC is
read only, write operations are ig-
nored.
H_RESET or S_RESET, or by
setting the STOP bit.
Description
Description
Description
encountered
MFC
RCC
by
is
is
H_RESET
cleared
cleared
P R E L I M I N A R Y
by
the
Am79C971
by
by
or
0
CSR124: Test Register 1
This register is used to place the Am79C971 controller
into various test modes. The Runt Packet Accept is the
only user accessible test mode. All other test modes are
for AMD internal use only.
Bit
31-16 RES
15-4
3
2-0
CSR125: MAC Enhanced Configuration Control
Bit
RCVALGN
RES
RPA
RES
Name
Name
Receive Packet Align. When set,
this bit forces the data field of ISO
8802-3 (IEEE/ANSI 802.3) pack-
ets to align to 0. MOD 4 address
boundaries (i.e., DWord aligned
addresses). It is important to note
that this feature will only function
correctly if all receive buffer
boundaries are DWord aligned
and all receive buffers have 0
MOD 4 lengths. In order to ac-
complish the data alignment, the
Am79C971 controller simply in-
serts two bytes of random data at
the beginning of the receive pack-
et (i.e., before the ISO 8802-3
(IEEE/ANSI 802.3) destination
address field). The MCNT field
reported to the receive descriptor
will not include the extra two
bytes.
Read/Write accessible always.
RCVALGN
H_RESET or S_RESET and is
not affected by STOP.
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Written as
zeros and read as undefined.
Runt Packet Accept. This bit
forces the Am79C971 controller
to accept runt packets (packets
shorter than 64 bytes).
Read accessible always; write
accessible only when STOP is
set to 1. RPA is cleared by
H_RESET or S_RESET and is
not affected by STOP.
Reserved locations. Written as
zeros and read as undefined.
Description
Description
is
cleared
147
by