AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 129

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

1
0
CSR8: Logical Address Filter 0
Bit
31-16
15-0
CSR9: Logical Address Filter 1
Bit
31-16
15-0 LADRF[31:16] Logical Address Filter, LADRF-
LADRF[15:0] Logical Address Filter, LADRF-
MIIPDTINT MII PHY Detect Transition Inter-
MIIPDTINTE MII PHY Detect Transition Inter-
Name
RES
Name
RES
rupt. The MII PHY Detect Transi-
tion Interrupt is set by the
Am79C971 controller whenever
the MIIPD bit (BCR32, bit 14)
transitions from 0 to 1 or vice ver-
sa.
Read/Write accessible always.
MIIPDTINT is cleared by the host
by writing a 1. Writing a 0 has no
effect. MIIPDTINT is cleared by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
rupt Enable. If MIIPDTINTE is set
to 1, the MIIPDTINT bit will be
able to set the INTR bit.
Read/Write accessible always.
MIIPDTINTE is set to 0 by
H_RESET and is not affected by
S_RESET or setting the STOP
bit.
zeros and read as undefined.
[15:0]. The content of this register
is undefined until loaded from the
initialization block after the INIT
bit in CSR0 has been set or a di-
rect register write has been per-
formed on this register.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
zeros and read as undefined.
[31:16]. The content of this regis-
ter is undefined until loaded from
the initialization block after the
INIT bit in CSR0 has been set or
Description
Reserved locations. Written as
Description
Reserved locations. Written as
Am79C971
CSR10: Logical Address Filter 2
Bit
31-16 RES
15-0 LADRF[47:32] Logical
CSR11: Logical Address Filter 3
Bit
31-16 RES
15-0 LADRF[63:48] Logical
CSR12: Physical Address Register 0
Bit
31-16 RES
Name
Name
Name
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET, or
STOP.
a direct register write has been
performed on this register.
Description
zeros and read as undefined.
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
Description
zeros and read as undefined.
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on this
register.
Description
zeros and read as undefined.
Reserved locations. Written as
Reserved locations. Written as
Reserved locations. Written as
Address
Address
Filter,
Filter,
129