AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 47

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

If 512 bits or more have been transmitted, the message
will have the current FCS inverted and appended at the
next byte boundary to guarantee an FCS error is de-
tected at the receiving station.
APERREN does not affect the reporting of address
parity errors or data parity errors that occur when the
Am79C971 controller is the target of the transfer.
Initialization Block DMA Transfers
During execution of the Am79C971 controller bus mas-
ter initialization procedure, the Am79C971 microcode
will repeatedly request DMA transfers from the BIU.
During each of these initialization block DMA transfers,
the BIU will perform two data transfer cycles reading
one DWord per transfer and then it will relinquish the
bus. When SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the
initialization block is organized as 32-bit software struc-
tures), there are seven DWords to transfer during the
bus master initialization procedure, so four bus master-
ship periods are needed in order to complete the initial-
ization sequence. Note that the last DWord transfer of
the last bus mastership period of the initialization se-
quence accesses an unneeded location. Data from this
transfer is discarded internally. When SSIZE32 is
cleared to 0 (i.e., the initialization block is organized as
16-bit software structures), then three bus mastership
periods are needed to complete the initialization se-
quence.
The Am79C971 supports two transfer modes for read-
ing the initialization block: non-burst and burst mode,
with burst mode being the preferred mode when the
Am79C971 controller is used in a PCI bus application.
See Figure 23 and Figure 24.
When BREADE is cleared to 0 (BCR18, bit 6), all initial-
ization block read transfers will be executed in non-
burst mode. There is a new address phase for every
data phase. FRAME will be dropped between the two
transfers. The two phases within a bus mastership pe-
riod will have addresses of ascending contiguous or-
der.
When BREADE is set to 1 (BCR18, bit 6), all initializa-
tion block read transfers will be executed in burst mode.
AD[1:0] will be 0 during the address phase indicating a
linear burst order.
Descriptor DMA Transfers
Am79C971 microcode will determine when a descrip-
tor access is required. A descriptor DMA read will con-
sist of two data transfers. A descriptor DMA write will
consist of one or two data transfers. The descriptor
DMA transfers within a single bus mastership period
will always be of the same type (either all read or all
write).
During descriptor read accesses, the byte enable sig-
nals will indicate that all byte lanes are active. Should
Am79C971
some of the bytes not be needed, then the Am79C971
controller will internally discard the extraneous informa-
tion that was gathered during such a read.
The settings of SWSTYLE (BCR20, bits 7-0) and
BREADE (BCR18, bit 6) affect the way the Am79C971
controller performs descriptor read operations.
When SWSTYLE is set to 0 or 2, all descriptor read op-
erations are performed in non-burst mode. The setting
of BREADE has no effect in this configuration. See Fig-
ure 25.
When SWSTYLE is set to 3, the descriptor entries are
ordered to allow burst transfers. The Am79C971 con-
troller will perform all descriptor read operations in
burst mode, if BREADE is set to 1. See Figure 26.
Table 4 shows the descriptor read sequence.
During descriptor write accesses, only the byte lanes
which need to be written are enabled.
SWSTYLE
BCR20[7:0]
0
2
3
3
Table 4. Descriptor Read Sequence
BREADE
BCR18[6]
X
X
0
1
AD Bus Sequence
Address = XXXX XX00h
Turn around cycle
Data = MD1[31:24],
MD0[23:0]
Idle
Address = XXXX XX04h
Turn around cycle
Data = MD2[15:0], MD1[15:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Idle
Address = XXXX XX00h
Turn around cycle
Data = MD0[31:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Idle
Address = XXXX XX08h
Turn around cycle
Data = MD0[31:0]
Address = XXXX XX04h
Turn around cycle
Data = MD1[31:0]
Data = MD0[31:0]
47