AM79C971VCW Advanced Micro Devices, AM79C971VCW Datasheet - Page 86

• Manufacturer Part Number: AM79C971VCW
• Description: PCnet-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus
• Manufacturer: Advanced Micro Devices

After the Expansion ROM is enabled, the Am79C971
controller will claim all memory read accesses with an
address between ROMBASE and ROMBASE + 1M - 4
(ROMBASE, PCI Expansion ROM Base Address reg-
ister, bits 31-20). The address output to the Expansion
ROM is the offset from the address on the PCI bus to
ROMBASE. The Am79C971 controller aliases all ac-
cesses to the Expansion ROM of the command types
Memory Read Multiple and Memory Read Line to the
basic Memory Read command.
Since setting MEMEN also enables memory mapped
access to the I/O resources, attention must be given to
the PCI Memory Mapped I/O Base Address register,
before enabling access to the Expansion ROM. The
host must set the PCI Memory Mapped I/O Base Ad-
dress register to a value that prevents the Am79C971
controller from claiming any memory cycles not in-
tended for it.
During the boot procedure, the system will try to find an
Expansion ROM. A PCI system assumes that an Ex-
pansion ROM is present when it reads the ROM signa-
ture 55h (byte 0) and AAh (byte 1). A design without
Expansion ROM can guarantee that the Expansion
ROM detection fails by connecting two adjacent EBD
pins together and tying them high or low.
86
Figure 43. EPROM Only Configuration for the Expansion Bus (64K EPROM)
Am79C971
EBUA_EBA[7:0]
EBDA[15:8]
AS_EBOE
EBD[7:0]
ERAMCS
EROMCS
EBWE
Am79C971
Direct Flash Access
Am79C971 controller supports Flash as an Expansion
ROM device, as well as providing a read/write data
path to the Flash. The Am79C971 controller will sup-
port up to 1 Mbyte of Flash on the Expansion Bus. The
Flash is accessed by a read or write to the Expansion
Bus Data port (BCR30). The user must load the upper
address EPADDRU (BCR 29, bits 3-0) and then set the
FLASH (BCR29, bit 15) bit to a 1. The Flash read/write
utilizes the PCI clock instead of the EBCLK during all
accesses. EPADDRU is not needed if the Flash size is
64K or less, but still must be programmed. The user will
then load the lower 16 bits of address, EPADDRL (BCR
28, bits 15-0).
Flash/EPROM Read
A read to the Expansion Bus Data Port (BCR30) will
start a read cycle on the Expansion Bus Interface. The
Am79C971 controller will drive EBUA_EBA[7:0] with
the most significant address byte at the same time the
Am79C971 controller will drive AS_EBOE high to
strobe the address in the external ‘374 (D flip-flop). On
the next clock, the Am79C971 controller will drive
EBDA[15:8] and EBUA_EBA[7:0] with the middle and
least significant address bytes.
A[15:8]
A[7:0]
DQ[7:0]
CS
OE
EPROM
20550D-46