IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 96

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

5–8
Using Frame Mode
DSP Builder Standard Blockset User Guide
Simulation using burst mode works the same as single clock mode, but DSP Builder
introduces a latency of the specific packet size on the output signals of the HIL blocks.
As a consequence, feedback-loops may not work properly unless you enclose them in
the HIL block, and some intervention may be necessary when comparing or
visualizing HIL simulation results.
The HIL block uses software buffers to send and receive from the hardware, so you
can change these buffer sizes without recompiling the HIL function.
To activate frame mode turn on the Frame Mode option in the Hardware in the loop
dialog box
and provides a way to partially compensate for the burst mode output delay.
To use frame mode, the following conditions must be true:
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■
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In frame mode, the HIL block monitors the input synchronization and output
synchronization signals and increases the output delay to align the output data
frames with the input data frames. For example, if the burst length is 1024 and the
latency 3, the delay is 1027 (1024 + 3) without frame mode or 2048 (aligned to the next
frame) with frame mode on.
The burst packet size in frame mode must be a multiple of the frame packet interval.
For example, if packets arrive every 100 clocks, you can use a frame burst size of N ×
100 clocks (N positive integer).
Figure 5–7
for the Stratix II target device family, with a transform length of 64 points, data
precision of 16 bits, and twiddle precision of 16 bits.
The HIL block works with the concept of blocks of data (frames).
DSP Builder provides the data frames at regular intervals.
There is one input synchronization and one output synchronization signal
available.
The latency between the input synchronization and output synchronization
signals is constant.
illustrates a DSP Builder design with a FFT MegaCore function configured
(Figure 5–6 on page
Preliminary
5–7). Frame mode builds on the burst functionality
© June 2010 Altera Corporation
Burst and Frame Modes
Chapter 5: Using HIL