IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 258

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–12
Table 3–19. Complex Product Block Parameters
Table 3–20. Complex Product Block I/O Formats (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Bus Type
[number of bits].[]
[].[number of bits]
Pipeline Register
Use Enable Port
Use Asynchronous
Clear Port
Use Dedicated
Circuitry
I
I/O
I1
I2
I3
I4
Name
Real([L1].[R1])Imag([L1].[R1])
Real([L2].[R2])Imag([L2].[R2])
[1]
[1]
Simulink (2),
Inferred, Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0 (Parameterizable)
>= 0 (Parameterizable)
No Register, Inputs Only,
Multiplier Only, Adder Only,
Inputs and Multiplier,
Inputs and Adder,
Multiplier and Adder,
Inputs Multiplier and Adder
On or Off
On or Off
On or Off
Table 3–18
Table 3–18. Complex Product Block Inputs and Outputs
Table 3–19
Table 3–20
(3)
a
b
ena
aclr
r
Signal
I1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
I2Real: in STD_LOGIC_VECTOR({LP2 + RP2 - 1} DOWNTO 0)
I2Imag: in STD_LOGIC_VECTOR({LP2 + RP2 - 1} DOWNTO 0)
I3: in STD_LOGIC
I4: in STD_LOGIC
Value
shows the Complex Product block inputs and outputs.
shows the Complex Product block parameters.
shows the Complex Product block I/O formats.
Input
Input
Input
Input
Output
Direction
Specify the bus number format that you want to use. Inferred means
that the format is automatically set by the format of the connected
signal.
Specify the number of bits to the left of the binary point.
Specify the number of bits to the right of the binary point. This option
applies only to signed fractional formats.
Specify the elements that you want pipelined. The clock enable and
asynchronous clear ports are available only if the block is registered.
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
If you target devices that support DSP blocks, turn on to implement the
functionality in DSP blocks instead of logic elements.
Preliminary
Complex operand a.
Complex operand b.
Optional clock enable.
Optional asynchronous clear.
Result.
(Note 1)
VHDL
Description
Description
Chapter 3: Complex Type Library
© June 2010 Altera Corporation
Complex Product
Type
Implicit
(4)