IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 338

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

8–2
Table 8–1. External RAM Block Inputs and Outputs (Part 2 of 2)
Table 8–2. External RAM Block Parameters
Figure 8–1. External RAM Block Example
DSP Builder Standard Blockset Libraries
ReadWaitRequest
ReadDataValid
Data Width
Address Width
Wait States Per Write
Maximum Latency
Size
Offset
Notes to
(1) The size added to the offset must be less than 2
Name
Table 8–2
Signal
Table 8–2
Figure 8–1
8, 16, 32, 64,
or 128
1–32
0–10
1–255
1–2
1–2
Output
Output
Direction
n
n
Value
(Note 1)
(Note 1)
shows the External RAM block parameters.
shows an design example with the External RAM block.
Stalls the interface when the Avalon-MM interface cannot respond immediately to a
read request.
Marks the rising clock edge when ReadData is asserted. Indicates that valid data
is present on the ReadData lines.
Specifies the number of bits for the data. No other values are supported. 64 and
128 bit data widths require a Simulink fixed-point license.
Specifies the number of bits n for the address.
Specifies a fixed number of wait states for each write transfer.
Specifies the latency for pipelined read transfers.
Specifies the total size of the RAM in bytes (the number of addresses when you
use a range of addresses).
Specifies an offset for the RAM start address (the start address when you use a
range of addresses.
n
where n is the address width.
Preliminary
Description
Description
© June 2010 Altera Corporation
Chapter 8: Simulation Library
External RAM