IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 366

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–26
Table 9–37. True Dual-Port RAM Block Parameters (Part 2 of 2)
DSP Builder Standard Blockset Libraries
Memory Block Type
Use DONT_CARE when
reading from and writing
to the same address
Initialization
Input HEX File
MATLAB Array
Register output Ports
Use Enable Port
Clock Phase Selection
Name
AUTO, M512, M4K,
M-RAM, M9K,
MLAB, M144K
On or Off
Blank, From HEX file,
From MATLAB array
User defined
User defined
(Parameterizable)
On or Off
On or Off
User Defined
Value
The FPGA RAM memory block type. Some memory types are not
available for all device types. If you specify M-RAM, the RAM is always
initialized to unknown in the hardware and simultaneous read/writes to
the same address give unknown in hardware. The unknowns are not
modeled in Simulink, and comparisons with ModelSim shows
differences.
If the memory block type is set to AUTO, setting DONT_CARE gives more
flexibility in RAM block placement. If the implementation is set to MLAB,
the design uses fewer external registers, because the output is not double
registered, and the resulting memory block can often be run at a higher
f
the same address is unpredictable. In ModelSim simulation, unknowns
(X) are output when reading from and writing to the same address. The
Simulink simulation is unchanged whether or not you use this option, but
a warning message issues on every simultaneous read/write to the same
address. If you compare the simulation results to ModelSim, you see
mismatches associated with any read/write to the same address events.
When this option is set, ensure that the same address is not read from
and written to at the same time or that your design does not depend on
the read output in these circumstances. By default this option is off, and
data is always read before write.
Specify the initialization. If Blank is selected, the contents of the RAM
are pre-initialized to zero.
Specify the name of an .hex file, which must be in your DSP Builder
working directory. For example: input.hex.
DSP Builder supports 32-bit addressing with extended linear address
records in the .hex file.
Specify a one-dimensional MATLAB array with a length less than or equal
to the number of words. For example: [0:1:15]
Turn on to register the output ports.
Turn on to use the optional clock enable input (ena).
Specify the phase selection with a binary string, where a 1 indicates the
phase in which the block is enabled. For example:
Max
1—The block is always enabled and captures all data passing through
the block (sampled at the rate 1).
10—The block is enabled every other phase and every other data
(sampled at the rate 1) passes through.
0100—The block is enabled on the second phase of and only the
second data of (sampled at the rate 1) passes through. That is, the
data on phases 1, 3, and 4 do not pass through the block.
. However, the output in hardware when reading from and writing to
Preliminary
Description
© June 2010 Altera Corporation
Chapter 9: Storage Library
True Dual-Port RAM