IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 371

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 10: State Machine Functions Library
State Machine Table
Figure 10–2. Example With the State Machine Editor Block
State Machine Table
© June 2010 Altera Corporation
f
1
For more information, refer to the Using the State Machine Editor Block chapter in the
DSP Builder Standard Blockset User Guide
Handbook.
The State Machine Table block represents a one-hot Moore-style state machine
where the output is equal to the current state
Figure 10–3. Moore Style State Machine
The default state machine has five inputs and five states. Each state is represented by
an output.
While the state machine is operating, an output is assigned a logic level 1 if its
respective state is equal to the current state. All other outputs are assigned a logic
level 0. The inputs and outputs are represented as integers in Simulink. In VHDL, the
input and output are represented as standard logic vectors.
The State Machine Table block is not available on Linux and is deprecated on
Windows. Use the
State Machine Editor
Preliminary
section in volume 2 of the DSP Builder
(Figure
block in new designs.
10–3).
DSP Builder Standard Blockset Libraries
10–3