IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 339

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Simulation Library
Multiple Port External RAM
Multiple Port External RAM
Table 8–3. Multiple Port External RAM Block Inputs and Outputs
© June 2010 Altera Corporation
WriteDataN
WriteAddressN
WriteEnableN
WriteBurstCountN
ReadAddressN
ReadEnableN
ReadBurstCountN
WriteWaitRequestN Output
ReadDataN
ReadDataValidN
ReadWaitRequestN
Signal
f
f
1
The Multiple Port External RAM block is a simulation model of a multiple port
external RAM block. It stores and retrieves data from a range of addresses and is
compatible with the Avalon-MM interface.
For information about the Avalon-MM interface, refer to
This block is not cycle-accurate and a warning issues if you use it in a gate level
(cycle-accurate) simulation.
If 64 or 128 bit data width is specified, the block attempts to use a Simulink
fixed-point license. If you do not have a Simulink fixed-point license., you can only
use 8, 16 or 32 bit data widths.
For information about fixed-point licenses, refer to the Simulink Help.
This is a simulation only block, and does not generate any HDL when you run
Compiler.
The ports on the block symbol update when you change the number of write or read
interfaces. However, the port names do not automatically show on the block symbol.
To display the updated block symbol correctly, perform the following steps:
1. Click on the block, point to Link Options in the popup menu and click Break
2. While the block is still selected, run the following command in MATLAB:
Table 8–3
Link.
alt_dspbuilder_update_external_RAM
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Direction
shows the Multiple Port External RAM block inputs and outputs.
Data lines for write transfers on port N.
Address lines for write transfers on port N.
Write enable for transfers on port N.
Write burst count for transfers on port N.
Address lines for read transfers on port N.
Read enable for transfers on port N.
Read burst count for transfers on port N.
Stalls the interface when the Avalon-MM interface cannot respond immediately to a
write request on port N.
Data lines for read transfers on port N.
Marks the rising clock edge when ReadDataN is asserted. Indicates that valid
data is present on the ReadDataN lines.
Stalls the interface when the Avalon-MM interface cannot respond immediately to a
read request on port N.
Preliminary
Description
Avalon Interface
DSP Builder Standard Blockset Libraries
Specifications.
Signal
8–3