IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 256

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–10
Table 3–14. Complex Delay Block I/O Formats (Part 2 of 2)
Figure 3–5. Complex Delay Block Example
Complex Multiplexer
Table 3–16. Complex Multiplexer Block Parameters
DSP Builder Standard Blockset Libraries
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
Number of Input Data Lines
Number of Pipeline Stages
Use Enable Port
Use Asynchronous Clear Port
One Hot Select Bus
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
[L].[R]
Real([L1].[R1])Imag([L1].[R1])
Table
Simulink (2),
is an input port. O1
Name
3–14:
Figure 3–5
The Complex Multiplexer block multiplexes N complex inputs to one complex
output. The select port sel is a non-complex scalar.
Table 3–15
Table 3–15. Complex Multiplexer Block Inputs and Outputs
Table 3–16
(3)
sel
0 to N—1
ena
aclr
unnamed
[L].[R]
Signal
is an output port.
O1Real: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
O1Imag: in STD_LOGIC_VECTOR({LP1 + RP1 - 1} DOWNTO 0)
>= 2
>= 0
On or Off
On or Off
On or Off
Value
shows an example with the Complex Delay block.
shows the Complex Multiplexer block inputs and outputs.
shows the Complex Multiplexer block parameters.
Input
Input
Input
Input
Output
Direction
Number of complex input data lines.
Specify the delay length of the block.
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
Turn on to use one-hot selection for the select signal instead of full binary.
Preliminary
Non-complex select line.
Complex inputs.
Optional clock enable.
Optional asynchronous clear.
Result.
(Note 1)
VHDL
Description
Description
Chapter 3: Complex Type Library
© June 2010 Altera Corporation
Implicit
Complex Multiplexer
Type
(4)