IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 209

DSP BUILDER SOFTWARE

IPT-DSPBUILDER

Manufacturer Part Number
IPT-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Datasheet

Specifications of IPT-DSPBUILDER

Function
DSP Builder
License
Initial License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
© June 2010 Altera Corporation
The Arithmetic library contains two’s complement signed arithmetic blocks such as
multipliers and adders. Some blocks have a Use Dedicated Circuitry option, which
implements functionality into dedicated hardware in the Altera FPGA devices (that is,
in the dedicated DSP blocks of these devices).
The Arithmetic library contains the following blocks:
Barrel Shifter
Bit Level Sum of Products
Comparator
Counter
Differentiator
Divider
DSP
Gain
Increment Decrement
Integrator
Magnitude
Multiplier
Multiply Accumulate
Multiply Add
Parallel Adder Subtractor
Pipelined Adder
Product
SOP Tap
Square Root
Sum of Products
Preliminary
2. Arithmetic Library
DSP Builder Standard Blockset Libraries

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