IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 195

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 1: AltLab Library
HDL Import
HDL Import
Table 1–5. HDL Import Block Parameters (Part 1 of 2)
© June 2010 Altera Corporation
Import HDL
Add
Remove
Up, Down
Enter name of top
level design entity
Import Quartus II
Project
Browse
Name
1
.qpf file
On or Off
.v or .vhd file Click to browse for one or more VHDL files or Verilog HDL files.
Entity name
On or Off
Use the HDL Import block to import existing blocks implemented in HDL into DSP
Builder. Individually specify the VHDL or Verilog HDL files or define in a Quartus
project file (.qpf).
You must save your model file before you can import HDL with the HDL Import
block.
When you click Compile, a simulation file generates and the block in your model
configures with the required input and output ports. The Quartus II software
synthesizes the imported HDL or project as a netlist of megafunctions, LPM functions,
and gates.
DSP Builder may explicitly instantiate the megafunctions and LPM functions in the
imported files, or the Quartus II software may infer them. The netlist then compiles
into a binary simulation netlist for use by the HDL simulation engine in DSP Builder.
When simulating imported VHDL in ModelSim, which includes FIFO buffers, there
may be Xs in the simulation results, which may give a mismatch with the Simulink
simulation. You should use the FIFO buffer carefully to avoid any overflows or
underflows. Examine and eliminate any warnings of Xs that ModelSim reports during
simulation before you compare to the Simulink results.
The simulator supports many of the common megafunctions and LPM functions
although it does not support some. If DSP Builder encounters an unsupported
function, it issues an error message after you click Compile and it cannot import the
HDL. However, you may be able to rewrite the HDL so that the Quartus II software
infers a different megafunction or LPM function.
Table 1–5
Value
—
—
shows the parameters for the HDL Import block.
You can import individual HDL files when this option is on.
Click to remove the selected file from the list.
Click to change the compilation order by moving the selected HDL file up or down the
list. The file order is not important when you use the Quartus II software but may be
significant when you use other downstream tools (such as ModelSim).
Specifies the name of the top level entity in the imported HDL files.
When this option is on, you can specify the HDL to import with a Quartus II project file
(.qpf). DSP Builder imports the current HDL configuration. To import a different
revision, specify the required revision in the Quartus II software. The source files that
the Quartus II project uses must be in the same directory as your model file or be
explicitly referenced in the Quartus II settings file (.qsf). Error messages issue for any
entities that DSP Builder cannot find. Refer to the Quartus II documentation for
information about setting the current revision of a project and how to explicitly
reference the source files in your design.
Click to browse for a Quartus II project file.
Preliminary
Description
DSP Builder Standard Blockset Libraries
®
1–5
II