IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 213

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 2: Arithmetic Library
Comparator
Figure 2–2. Bit Level Sum of Products Block Example
Comparator
Table 2–9. Comparator Block I/O Formats (Part 1 of 2)
© June 2010 Altera Corporation
I
I/O
I1
I2
[L1].[R1]
[L2].[R2]
Simulink (2),
(3)
Figure 2–2
The Comparator block compares two Simulink signals and returns a single bit. The
Comparator block implicitly understands the input data type (for example, signed
binary or unsigned integer) and produces a single-bit output.
Table 2–7
Table 2–7. Comparator Block Inputs and Outputs
Table 2–8
Table 2–8. Comparator Block Parameters
Table 2–9
a
b
<unnamed>
Operator
Name
Signal
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I1: in STD_LOGIC_VECTOR({L2 + R2 - 1} DOWNTO 0)
shows the Comparator block inputs and outputs.
shows the Comparator block parameters.
shows the Comparator block I/O formats.
shows an example with the Bit Level Sum of Products block.
a == b,
a ~= b,
a < b,
a <= b,
a >= b,
a > b
Value
Input
Input
Output
Direction
Preliminary
(Note 1)
Operand a.
Operand b.
Result.
The operation you want to perform on the two buses.
VHDL
Description
Description
DSP Builder Standard Blockset Libraries
Implicit
Implicit
Type
(4)
2–5