IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 198

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

1–8
Table 1–9. HDL Input Block I/O Formats (Part 2 of 2)
HDL Output
Table 1–10. HDL Output Block Parameters
Table 1–11. HDL Output Block I/O Formats
DSP Builder Standard Blockset Libraries
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
Bus Type
[number of bits].[]
[].[number of bits]
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
I1
O1
[L].[R]
[L].[R]
Name
[L1].[R1]
[LP].[RP]
Table
[LP].[RP]
Table
Simulink (2),
Simulink (2),
is an input port. O1
is an input port. O1
1–9:
1–11:
Signed Integer,
Signed Fractional,
Unsigned Integer,
Single Bit
>= 0
(Parameterizable)
>= 0
(Parameterizable)
(3)
(3)
The HDL Output block should be connected directly to an output node in a
subsystem. Use with the
black-box simulation.
The type and bit width must match the type and bit width on the corresponding
output port in the HDL file referenced by the HDL Entity block. HDL Output
blocks are automatically generated by the
Table 1–10
Table 1–11
[L].[R]
[L].[R]
Value
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
I1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: out STD_LOGIC_VECTOR({LP + RP - 1} DOWNTO 0)
is an output port.
is an output port.
shows the HDL Output block I/O formats.
shows the HDL Output block parameters.
The number format of the bus.
Specify the number of bits to the left of the binary point, including the sign bit.
This parameter does not apply to single-bit buses.
Specify the number of bits to the right of the binary point. This parameter applies
only to signed fractional buses.
(Note 1)
Subsystem Builder
(Note 1)
Preliminary
VHDL
VHDL
Subsystem Builder
Description
and HDL Entity blocks for
© June 2010 Altera Corporation
block.
Chapter 1: AltLab Library
Explicit
Implicit - Optional
Explicit
Type
Type
HDL Output
(4)
(4)