IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 349

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
Dual-Port RAM
Table 9–11. Dual-Port RAM Block Parameters (Part 2 of 2)
Table 9–12. Dual-Port RAM Block I/O Formats
Figure 9–4. Dual-Port RAM Block Example
© June 2010 Altera Corporation
Clock Phase Selection
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
I5
O1
[L].[R]
[L1].[R1]
[L2].[0]
[L2].[0]
[1]
[1]
[L1].[R1]
Table
Name
Simulink (2),
is an input port. O1
9–12:
Table 9–12
Figure 9–4
(3)
User Defined
[L].[R]
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0)
I3: in STD_LOGIC_VECTOR({L3 - 1} DOWNTO 0)
I4: in STD_LOGIC
I5: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
Value
shows the Dual-Port RAM block I/O formats.
shows an example with the Dual-Port RAM block.
(Note 1)
Specify the phase selection with a binary string, where a 1 indicates the
phase in which the block enables. For example:
1—The block is always enabled and captures all data passing through
the block (sampled at the rate 1).
10—The block is enabled every other phase and every other data
(sampled at the rate 1) passes through.
0100—The block is enabled on the second phase of and only the
second data of (sampled at the rate 1) passes through. That is, the
data on phases 1, 3, and 4 do not pass through the block.
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Type
Explicit
Explicit
(4)
9–9