IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 58

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–14
Figure 3–14. 1000 as Opposed to 0100 Phase Delay
Using the PLL Block
DSP Builder Standard Blockset User Guide
f
Figure 3–14
on the 1000 and 0100 phases, respectively.
DSP Builder maps the PLL block to the hardware device PLL. The number of PLL
internal clock outputs that each device family supports depends on the specific device
packaging.
For information about the built-in PLLs, refer to the device handbook for the device
family you are targeting.
Figure 3–15
Figure 3–15. MultipleClockDelay.mdl
compares the scopes for the Delay block operating at a one quarter rate
shows an example of multiple-clock domain support using the PLL block.
Preliminary
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
Frequency Design Rules