IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 160

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

11–6
DSP Builder Standard Blockset User Guide
2. Click the Design Rule Check tab. You can use this tab to verify that the state
Figure 11–4. State Machine Builder Design Rule Check Tab
3. To save the changes made to your state machine, click OK.
Figure 11–5. fifo_controller Block After Closing the State Machine Table
machine you defined in the previous steps does not violate any of the design rules.
Click Analyze to evaluate the design rules for your state machine. If a design rule
is violated, an error message, highlighted in red, is listed in the Analysis Results
box. If error messages appear in the analysis results, fix the errors and rerun the
analysis until no error messages appear before simulating and generating VHDL
for your design.
Analyze.
The State Machine Builder dialog box closes and returns you to your Simulink
design file. The design file automatically updates with the input and output names
defined in the previous steps.
1
Figure 11–5
You may need to resize the block to ensure that the input and state names
do not overlap and display correctly.
shows the updated fifo_controller block.
Figure 11–4
Preliminary
shows the Design Rule Check tab after clicking
Chapter 11: Using the State Machine Library
Using the State Machine Table Block
© June 2010 Altera Corporation