IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 409

DSP BUILDER SOFTWARE

IPT-DSPBUILDER

Manufacturer Part Number
IPT-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Datasheet

Specifications of IPT-DSPBUILDER

Function
DSP Builder
License
Initial License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
AltLab
Arithmetic
© June 2010 Altera Corporation
This appendix lists the blocks in each of the libraries in the Altera DSP Builder
blockset.
The AltLab library includes the following blocks:
The Arithmetic library includes the following blocks:
BP (Bus Probe)
Clock
Clock_Derived
Display Pipeline Depth
HDL Entity
HDL Import
HDL Input
HDL Output
HIL (Hardware in the Loop)
Quartus II Global Project Assignment
Quartus II Pinout Assignments
Resource Usage
Signal Compiler
SignalTap II Logic Analyzer
SignalTap II Node
Subsystem Builder
TestBench
VCD Sink
Barrel Shifter
Bit Level Sum of Products
Comparator
Counter
Differentiator
Divider
DSP
Preliminary
14. Categorized Block List
DSP Builder Standard Blockset Libraries

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