IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 286
IPT-DSPBUILDER
Manufacturer Part Number
IPT-DSPBUILDER
Description
DSP BUILDER SOFTWARE
Manufacturer
Altera
Type
DSPr
Datasheet
1.IPT-DSPBUILDER.pdf
(422 pages)
Specifications of IPT-DSPBUILDER
Function
DSP Builder
License
Initial License
Software Application
IP CORE, DSP BUILDER
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Supported Families
Arria GX, Arria II GX, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
Not applicable / Not applicable
- Current page: 286 of 422
- Download datasheet (6Mb)
4–24
Table 4–41. Single Pulse Block Parameters
Table 4–42. Single Pulse Block I/O Formats
Figure 4–16. Single Pulse Output Signal Types
DSP Builder Standard Blockset Libraries
Signal Generation Type
Impulse Length
Delay
Specify Clock
Clock
Use Enable Port
Use Synchronous Clear Port On or Off
I
O
Notes to
(1) I1
I/O
I1
I2
O1
[1]
[1]
[1]
[1]
Table
is an input port. O1
Simulink
Name
4–42:
(1)
Table 4–40. Single Pulse Block Inputs and Outputs
Table 4–41
Table 4–42
Figure
ena
sclr
<unnamed>
[1]
is an output port.
Signal
On or Off
Step Up,
Step Down,
Impulse
Integer
(Parameterizable)
Integer
(Parameterizable)
On or Off
User defined
(Parameterizable)
4–16. shows an example of a Single Pulse block.
I1: in STD_LOGIC
I2: in STD_LOGIC
O1: out STD_LOGIC
shows the Single Pulse block parameters.
shows the Single Pulse block I/O formats.
Value
Input
Input
output
Direction
Specify the type of single pulse.
Specify the number of clock cycles for which the output signal is
transitional from 0 to 1 for an Impulse type output.
Specify the number of clock cycles that occur before the pulse
transition.
Turn on to explicitly specify the clock name.
Specify the name of the required clock signal.
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (sclr).
Preliminary
Optional clock enable port.
Optional synchronous clear port.
Output port.
VHDL
Description
Description
Chapter 4: Gate & Control Library
© June 2010 Altera Corporation
Optional trigger
Optional reset
Type
—
Single Pulse
Related parts for IPT-DSPBUILDER
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: