IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 313

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 6: IO & Bus Library
Bus Builder
Table 6–5. Binary Point Casting Block I/O Formats (Part 2 of 2)
Figure 6–4. Binary Point Casting Block Example
Bus Builder
Table 6–6. Bus Builder Block Parameters (Part 1 of 2)
© June 2010 Altera Corporation
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
Bus Type
[number of bits].[] >= 0
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
[L].[R]
Name
[LO].[RO]
Table
Simulink (2),
is an input port. O1
6–5:
1
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
Figure 6–4
The Bus Builder block constructs an output bus from single-bit inputs. The output
bus is signed integer, unsigned integer, or signed binary fractional format. You can
specify the number of bits in each case.
The HDL mapping of the Bus Builder block is a simple wire.
The input MSB is at the bottom left of the symbol and the input LSB displays at the
top left of the symbol.
The Bus Builder block does not support sign extension. Instead use a an
block
Table 6–6
(3)
[L].[R]
Value
(Figure 6–3 on page
is an output port.
O1: out STD_LOGIC_VECTOR({LO + RO - 1} DOWNTO 0)
shows the Bus Builder block parameters.
shows a design example with the Binary Point Casting block.
The number format of the bus.
Specifies the number of bits to the left of the binary point, including the sign bit.
6–4).
Preliminary
(Note 1)
VHDL
Description
DSP Builder Standard Blockset Libraries
AltBus
Type
Explicit
(4)
6–5