IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 355

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
Parallel To Serial
Table 9–22. Parallel To Serial Block Parameters
Table 9–23. Parallel To Serial Block I/O Formats
© June 2010 Altera Corporation
Data Bus Type
[number of bits].[] >= 0
[].[number of bits] >= 0
Serial Bit Order
Repeat Last Bit
Until Next Load
Use Enable Port
Use Synchronous
Clear Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
O1
[L].[R]
Name
[L1].[R1]
[1]
[1]
[1]
[1]
Table
Simulink (2),
is an input port. O1
9–23:
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
(Parameterizable)
MSB First,
LSB First
On or Off
On or Off
On or Off
Table 9–21
Table 9–21. Parallel To Serial Block Inputs and Outputs
Table 9–22
Table 9–23
(3)
d
load
ena
sclr
sd
[L].[R]
Value
Signal
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
I4: in STD_LOGIC
O1: out STD_LOGIC
shows the Parallel To Serial block inputs and outputs.
shows the Parallel To Serial block parameters.
shows the Parallel To Serial block I/O formats.
The bus type format.
Specify the number of bits stored on the left side of the binary point.
Specify the number of bits stored on the right side of the binary point. This option
applies only to signed fractional formats.
Transmit the MSB or LSB first.
Turn on to repeat the last bit until the next load.
Turn on to use the clock enable input.
Turn on to use the synchronous clear port (sclr).
Input
Input
Input
Input
Output
Direction
(Note 1)
Preliminary
Parallel input port.
Load port.
Optional clock enable port.
Optional synchronous clear port.
Serial output port.
VHDL
Description
Description
DSP Builder Standard Blockset Libraries
Type
Explicit
Explicit
9–15
(4)