IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 281

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 4: Gate & Control Library
Logical Reduce Operator
Figure 4–12. Logical Bus Operator Block Example
Logical Reduce Operator
Table 4–32. Logical Reduce Operator Block Parameters (Part 1 of 2)
© June 2010 Altera Corporation
Bus Type
[number of bits].[] >= 0
Name
Inferred,
Signed Integer,
Signed Fractional,
Unsigned Integer
(Parameterizable)
Figure 4–12
The Logical Reduce Operator block performs logical reduction operations on a
bus such as AND, OR, XOR. The logical operation is applied bit-wise to the input bus to
give a single bit result.
Table 4–31
Table 4–31. Logical Reduce Operator Block Inputs and Outputs
Table 4–32
d
q
Value
Signal
shows the Logical Reduce Operator block inputs and outputs.
shows the Logical Reduce Operator block parameters.
shows an example with the Logical Bus Operator block.
Specify the bus number format that you want to use.
Specify the number of bits to the left of the binary point, including the sign bit.
Input
Output
Direction
Preliminary
Input data.
Output result.
Description
Description
DSP Builder Standard Blockset Libraries
4–19