IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 342

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–2
Delay
Table 9–2. Delay Block Parameters
Table 9–3. Delay Block I/O Formats (Part 1 of 2)
DSP Builder Standard Blockset Libraries
Number of Pipeline
Stages
Clock Phase
Selection
Use Enable Port
Use Synchronous
Clear Port
Reset To Constant
(Non-Zero) Value
Reset Value
I
I/O
I1
I2
I3
Name
[L1].[R1]
[1]
[1]
Simulink (2),
User Defined
(Parameterizable)
User Defined
On or Off
On or Off
On or Off
User Defined
(Parameterizable)
The Delay block delays the incoming data by an amount specified by the number of
pipeline stages. The block accepts any data type as inputs.
Table 9–1
Table 9–1. Delay Block Inputs and Outputs
Table 9–2
Table 9–3
(3)
<unnamed>
ena
sclr
<unnamed>
Value
Signal
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
shows the Delay block inputs and outputs.
shows the Delay block parameters.
shows the Delay block I/O formats.
Specify the pipeline length of the block. The delay must be greater than or equal to
1.
Specify the phase selection with a binary string, where a 1 indicates the phase in
which the Delay block is enabled. For example:
Turn on to use the clock enable input (ena).
Turn on to use the synchronous clear input (sclr).
Turn on to specify a non-zero reset value. Specifying a reset value increases the
hardware resources.
Specify the reset value.
1—The block is always enabled and captures all data passing through the block
(sampled at the rate 1).
10—The block is enabled every other phase and every other data (sampled at
the rate 1) passes through.
0100—The block is enabled on the second phase of and only the second data
of (sampled at the rate 1) passes through. That is, the data on phases 1, 3, and
4 do not pass through the delay block.
Input
Input
Input
Output
Direction
(Note 1)
Preliminary
Input data port.
Optional clock enable port.
Optional synchronous clear port.
Output data port.
VHDL
Description
Description
© June 2010 Altera Corporation
Chapter 9: Storage Library
Type
Implicit
Delay
(4)