IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 113

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 7: Using the Interfaces Library
Avalon-MM Interface Blocks
Figure 7–2. Avalon-MM Master Block Signals
Wrapped Blocks
© June 2010 Altera Corporation
The Avalon-MM Master and Avalon-MM Slave interface blocks allow you to
generate a SOPC Builder component in DSP Builder, but they do little to mask the
complexities of the interface. The Avalon-MM read and write FIFO blocks in the
Interfaces library provide a higher level of abstraction.
You can implement a typical DSP core that handles data in a streaming manner, with
the signals Data, Valid, and Ready. To provide a high level view, DSP Builder
provides you with configurable Avalon-MM Write FIFO and Avalon-MM Read
FIFO blocks for you to map Avalon-MM interface signals to this protocol.
Preliminary
DSP Builder Standard Blockset User Guide
7–5