IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 121

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 7: Using the Interfaces Library
Avalon-MM Interface Blocks Design Example
Figure 7–9. Including Your DSP Builder Design Module in SOPC Builder
© June 2010 Altera Corporation
5. Click the System Contents tab in SOPC Builder and set the following options:
a. Expand Memories and Memory Controllers.
b. Expand On-Chip and double-click On-Chip Memory (RAM or ROM).
c. Specify 30 KBytes for the Total Memory size.
d. Click Finish to add an on-chip RAM device to the system.
e. Double-click Nios II Processor in the System Contents tab to display the
f. Set the reset and exception vectors to use onchip_mem and click Finish to add
g. Expand Peripherals and Debug and Performance. Double-click on System ID
h. Expand Interface Protocols and Serial. Double-click on JTAG UART and click
i. Expand DSPBuilder Systems and double-click the topavalon_interface
MegaWizard interface.
the processor to your system with all other parameters set to their default
values.
Peripheral and click Finish to accept the default settings.
Finish to accept the default settings.
module to include it in your Nios II system
Preliminary
(Figure
DSP Builder Standard Blockset User Guide
7–9).
7–13