IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 354

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–14
Table 9–20. Memory Delay Block I/O Formats
Figure 9–7. Memory Delay Block Example
Parallel To Serial
DSP Builder Standard Blockset Libraries
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
<--------------- data values ---------------->|<- last bit repeated until next load ->
<--------------- data values ---------------->|<----- zeros until next load ---->
0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 1 ... 1
0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 0 ... 1 ... 0
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
O1
[L].[R]
[L1].[R1]
[1]
[1]
[L1].[R1]
Table
Simulink (2),
is an input port. O1
9–20:
Table 9–20
Figure 9–7
The Parallel To Serial block takes a bus input on load and outputs the
individual bits one cycle at a time with either the MSB or LSB first.
You can specify to continually output the last bit until the last load. For example, if
input is an 8-bit unsigned integer value 1 the output is:
Alternatively, if this option is off, you can output 0 after the data has finished, that is,
for the same example:
(3)
[L].[R]
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC
I3: in STD_LOGIC
O1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
shows the Memory Delay block I/O formats.
shows an example with the Memory Delay block.
(Note 1)
Preliminary
VHDL
... 1 ... 1 ............
... 0 ... 0 ............
© June 2010 Altera Corporation
Chapter 9: Storage Library
Parallel To Serial
Type
Implicit
Implicit
(4)