IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 358

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

9–18
Table 9–26. ROM Block I/O Formats
Figure 9–9. ROM Block Example
Serial To Parallel
DSP Builder Standard Blockset Libraries
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1[
I2
O1
[L].[R]
[1]
L1].[0]
[LPO].[RPO]
Table
Simulink (2),
is an input port. O1
9–26:
Table 9–26
Figure 9–9
.hex file.
The Serial To Parallel block implements a serial (input sd) to parallel bus
conversion (output d). Treat the input bit stream as either MSB first, or LSB first.
Table 9–27
Table 9–27. Serial To Parallel Block Inputs and Outputs
(3)
sd
ena
sclr
d
[L].[R]
Signal
is an output port.
I1: in STD_LOGIC_VECTOR({L1 - 1} DOWNTO 0)
I2: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({LPO + RPO - 1} DOWNTO 0)
shows the ROM block I/O formats.
shows an example with the ROM block that reads a 256×8 ramp waveform
shows the Serial To Parallel block inputs and outputs.
(Note 1)
Input
Input
Input
Output
Direction
Preliminary
Serial input port.
Optional clock enable port.
Optional synchronous clear port.
Parallel output port.
VHDL
Description
© June 2010 Altera Corporation
Chapter 9: Storage Library
Serial To Parallel
Type
Explicit
Explicit
(4)