IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 320

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–12
Extract Bit
Table 6–16. Extract Bit Block Parameters
Table 6–17. Extract Bit Block I/O Formats
Figure 6–10. Extract Bit Block Example
DSP Builder Standard Blockset Libraries
Bus Type
[number of bits].[]
[].[number of bits]
Select the Bit to be
Extracted From the Bus
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
O1
[L].[R]
[L1].[R1]
[1]
Table
Name
Simulink (2),
is an input port. O1
6–17:
The Extract Bit block reads a Simulink bus in the specified format and outputs the
single bit specified.
The selected bit is indexed starting from zero for the LSB and increasing to (total bit
width - 1) for the MSB.
Table 6–16
Table 6–17
Figure 6–10
(3)
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0 (Parameterizable) Specifies the number of bits to the left of the binary point, including the
>= 0 (Parameterizable) Specifies the number of bits to the right of the binary point.
>= 0 (Parameterizable) Specifies the input bit to extract.
[L].[R]
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
O1: out STD_LOGIC
Value
shows the Extract Bit block parameters.
shows the Extract Bit block I/O formats.
shows a design example with the Extract Bit block.
(Note 1)
Specifies the number format of the bus.
sign bit.
Preliminary
VHDL
Description
© June 2010 Altera Corporation
Chapter 6: IO & Bus Library
Type
Explicit
Explicit
Extract Bit
(4)