IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 330

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

6–22
Table 6–35. VCC Block I/O Formats
Figure 6–14. VCC Block Example
DSP Builder Standard Blockset Libraries
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
[L].[R]
[1]
Table
Simulink (2),
is an input port. O1
6–35:
Table 6–35
Figure 6–14
(3)
[L].[R]
is an output port.
O1: out STD_LOGIC
shows the VCC block I/O formats.
shows a design example with the VCC block.
(Note 1)
Preliminary
VHDL
© June 2010 Altera Corporation
Chapter 6: IO & Bus Library
Type
Explicit
(4)
VCC