IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 249

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Complex Type Library
Butterfly
Table 3–2. Butterfly Block Parameters (Part 2 of 2)
Table 3–3. Butterfly Block I/O Formats
Figure 3–1. Butterfly Block Example
© June 2010 Altera Corporation
W (real)
W (imaginary)
Dedicated Multiplier Circuitry
Use Enable Port
Use Asynchronous Clear Port
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
I5
O1
O2
[L].[R]
Real([Li].[0])Imag([Li].[0])
Real([Li].[0])Imag([Li].[0])
Real([Li].[0])Imag([Li].[0])
[1]
[1]
Real([Lo].[0])Imag([Li].[0])
Real([Lo].[0])Imag([Li].[0])
Table
is an input port. O1
Name
Simulink (2),
3–3:
Table 3–3
Figure 3–1
(3)
[L].[R]
is an output port.
User defined Specify the value of the real part of the constant W
User defined Specify the value of the imaginary part of the constant W.
Auto, Yes,
No
On or Off
On or Off
shows the Butterfly block I/O formats.
Value
shows an example with the Butterfly block.
I1Real: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0)
I1Imag: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0)
I2Real: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0)
I2Imag: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0)
I3Real: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0)
I3Imag: in STD_LOGIC_VECTOR({Li - 1} DOWNTO 0)
I4: in STD_LOGIC
I5: in STD_LOGIC
O1Real: out STD_LOGIC_VECTOR({Lo - 1} DOWNTO 0)
O1Imag: out STD_LOGIC_VECTOR({Lo - 1} DOWNTO 0)
O2Real: out STD_LOGIC_VECTOR({Lo - 1} DOWNTO 0)
O2Imag: out STD_LOGIC_VECTOR({Lo - 1} DOWNTO 0)
(Note 1)
For devices that support multipliers, a value of Auto specifies that the
choice is based on the width of the multiplier.
Turn on to use the clock enable input (ena).
Turn on to use the asynchronous clear input (aclr).
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit
Explicit
Type
(4)
3–3