IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 182

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

13–6
Warning if Input/Output Blocks Conflict with clock or aclr Ports
Wiring the Asynchronous Clear Signal
Error Issues when a Design Includes Pre-v7.1 Blocks
Creating an Input Terminator for Debugging a Design
DSP Builder Standard Blockset User Guide
f
1
A warning issues if an input or output port has the same name as a clock or reset
signal that your model uses. For example if your design has an input port aclr, this
name is the same name as the default system reset and the following warning issues
during analysis:
The input port renames during HDL conversion. If you want to keep the port aclr,
add a Clock block and use it to rename the reset port.
Wire the asynchronous clear signal with a register to make sure that the end of the
aclr cycle synchronizes with the clock
Figure 13–3. Wiring the Asynchronous Clear Signal
A design may not match the hardware if an asynchronous clear performs during
simulation because the aclr cycle may last several clocks - depending on clock speed
and the device.
An error of the following form issues if you attempt to simulate a design that includes
unupgraded pre-v7.1 blocks:
For information about upgrading your designs, refer to
Builder
If there is a problem somewhere in a design, disconnect some subsystems so that you
can analyze a small portion of your design. This procedure may cause bit width
propagation and inheritance problems.
You can avoid these problems by inserting a Non-synthesizable Output block
followed immediately by a Non-synthesizable Input block. This combination
functions as a temporary input terminator and you can remove them after you debug
your design.
Warning: aclrInputPortTest/aclr has been renamed to avoid conflict:
Data type mismatch. Input port 1 of '<old block>' expects a signal
of data type 'double'. However, it is driven by a signal of data type
'DSPB_Type'.
in the DSP Builder Handbook.
Preliminary
(Figure
aclr has been renamed to aclr_1:
13–3).
Volume 1: Introduction to DSP
© June 2010 Altera Corporation
Troubleshooting Issues
Chapter :