IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 122

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

7–14
Compiling the Quartus II Project
DSP Builder Standard Blockset User Guide
6. Click Generate to generate the SOPC Builder system. The system generation may
After the system generation in SOPC Builder completes, you can design the rest of
your Nios II embedded processor system using the standard Nios II embedded
processor design flow. Continue with this tutorial to exercise the system from
software using the Nios II processor.
To compile the Quartus II project, follow these steps:
1. On the Assignments menu in the Quartus II software, click Device to display the
2. On the Assignments menu, click Pins to open the Pin Planner and make pin
Table 7–1. Pin Assignments for the Stratix II and Cyclone II Development Boards
3. Close the Pin Planner.
4. On the Processing menu, click Start Compilation to compile the Quartus II project.
5. When the compilation completes, click Programmer on the Tools menu and click
6. Close the Quartus II Programmer window.
Node Name
Stratix II EP2S60 or EP2S60ES DSP Development Board
clk
reset_n
Cyclone II EP2C35 DSP Development Board
clk
reset_n
1
take several minutes.
Device page of the Settings dialog box and create the basic pin settings as follows:
a. In the Settings dialog box, click Device and Pin Options.
b. In the Device and Pin Options dialog box, click the Unused Pins tab, select As
c. Click OK to close the Settings dialog box.
assignments for clk and reset_n
board you are using).
1
You can ignore all other pin assignments for this tutorial.
Start in the Quartus II Programmer to program the FPGA device on your
development board.
input tri-stated and click OK.
If the memory device, Nios II processor, debug peripheral, interface
protocol, and DSP Builder system add in this order, you should not need to
set a base address. However, you can click Auto-Assign Base Addresses on
the System menu to automatically add a base address if necessary.
If the Location column does not display, right-click in the pin assignments
table and click Customize Columns to change the table display.
Direction
Input
Input
Input
Input
Preliminary
(Table
7–1) (depending on which development
Avalon-MM Interface Blocks Design Example
Location
PIN_AM17
PIN_AG19
PIN_N2
PIN_A14
Chapter 7: Using the Interfaces Library
© June 2010 Altera Corporation