IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 52

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

3–8
Figure 3–7. 3-Tap Filter with BusConversion to Control Bit Widths in Quartus II RTL Viewer
Frequency Design Rules
Single Clock Domain
DSP Builder Standard Blockset User Guide
f
1
For more information, refer to
This section describes the frequency design rules for single and multiple clock
domains.
If your design does not contain a PLL block or Clock_Derived block, DSP Builder
uses synchronous design rules to convert a Simulink design into hardware. All DSP
Builder registered blocks (such as the Delay block) operate on the positive edge of the
single clock domain, which runs at the system sampling frequency.
The clock pin is not graphically displayed in Simulink unless you use the Clock
block. However, when DSP Builder converts your design to VHDL it automatically
connects the clock pin of the registered blocks (such as the Delay block) to the single
clock domain of the system.
The default clock pin is named clock and there is also a default active-low reset pin
named aclr.
By default, Simulink does not graphically display the clock enable and reset input
pins of the DSP Builder registered blocks. When DSP Builder converts a design to
VHDL, it automatically connects these pins. You can access and drive these optional
ports by checking the appropriate option in the Block Parameters dialog box.
Simulink issues a warning if you are using an inappropriate solver for your model.
You should set the solver options to fixed-step discrete when you are using a single
clock domain.
For Simulink simulation, all DSP Builder blocks (including registered DSP Builder
blocks) use the sampling period specified in the Clock block. If there is no Clock
block in your design, the DSP Builder blocks use a sampling frequency of 1. You can
use the Clock block to change the Simulink sample period and the hardware clock
period.
Preliminary
“Fixed-Point Notation” on page
Chapter 3: Design Rules and Procedures
© June 2010 Altera Corporation
3–2.
Frequency Design Rules