IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 363

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 9: Storage Library
Single-Port RAM
Table 9–34. Single-Port RAM Block Parameters (Part 2 of 2)
Table 9–35. Single-Port RAM Block I/O Formats
© June 2010 Altera Corporation
Input HEX File
MATLAB Array
Register output
Port
Use Enable Port
Clock Phase
Selection
I
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
I1
I2
I3
I4
O1
[L].[R]
Name
[L1].[R1]
[L2].[0]
[1]
[1]
[L1].[R1]
Table
Simulink (2),
is an input port. O1
9–12:
User defined
User defined
(Parameterizable)
On or Off
On or Off
User Defined
Table 9–35
(3)
[L].[R]
Value
is an output port.
I1: in STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
I2: in STD_LOGIC_VECTOR({L2 - 1} DOWNTO 0)
I3: in STD_LOGIC
I4: in STD_LOGIC
O1: out STD_LOGIC_VECTOR({L1 + R1 - 1} DOWNTO 0)
shows the Single-Port RAM block I/O formats.
Specify the name of a .hex file that must be in your DSP Builder working
directory. For example: input.hex.
DSP Builder supports 32-bit addressing with extended linear address records
in the .hex file.
Specify a one-dimensional MATLAB array with a length less than or equal to
the number of words. For example: [0:1:15]
Turn on to register the output port.
Turn on to use the optional clock enable input (ena).
Specify the phase selection with a binary string, where a 1 indicates the phase
in which the block is enabled. For example:
1—The block is always enabled and captures all data passing through the
block (sampled at the rate 1).
10—The block is enabled every other phase and every other data (sampled
at the rate 1) passes through.
0100—The block is enabled on the second phase of and only the second
data of (sampled at the rate 1) passes through. That is, the data on phases
1, 3, and 4 do not pass through the delay block.
(Note 1)
Preliminary
VHDL
Description
DSP Builder Standard Blockset Libraries
Type
Explicit
Explicit
9–23
(4)