IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 259

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 3: Complex Type Library
Complex to Real-Imag
Table 3–20. Complex Product Block I/O Formats (Part 2 of 2)
Figure 3–7. Complex Product Block Example
Complex to Real-Imag
Table 3–22. Complex to Real-Imag Block Parameters
© June 2010 Altera Corporation
O
Notes to
(1) For signed integers and signed binary fractional numbers, the MSB is the sign bit.
(2) [L] is the number of bits on the left side of the binary point; [R] is the number of bits on the right side of the binary point. For signed or unsigned
(3) I1
(4) Explicit means that the port bit width information is a block parameter. Implicit means that the port bit width information is set by the datapath
Bus Type
[number of bits].[]
[].[number of bits]
I/O
integers R = 0, that is, [L].[0]. For single bits, R = 0, that is, [1] is a single bit.
bit width propagation mechanism. To specify the bus format of an implicit input port, use a Bus Conversion block to set the width.
O1
RI,R2))
Imag(2 x max(LI,L2)),(2 x max(RI,R
2))
[L].[R]
Real(2 x max(LI,L2)),(2 x max(
Table
Name
Simulink (2),
is an input port. O1
3–20:
Figure 3–7
The Complex to Real-Imag block constructs a fixed-point real and fixed-point
imaginary output from a complex input.
Table 3–21
Table 3–21. Complex to Real-Imag Block Inputs and Outputs
Table 3–22
(3)
c
r
i
Signed Integer,
Signed Fractional,
Unsigned Integer
>= 0
(Parameterizable)
>= 0
(Parameterizable)
[L].[R]
Signal
is an output port.
Value
O1Real: in STD_LOGIC_VECTOR({(2 x max(LI,L2)) + (2 x max(RI,R2)) -1}
DOWNTO 0)
O1Imag: in STD_LOGIC_VECTOR({(2 x max(LI,L2)) + (2 x max(RI,R2)) -1}
DOWNTO 0)
shows an example with the Complex Product block.
shows the Complex to Real-Imag block inputs and outputs.
shows the Complex to Real-Imag block parameters.
Input
Output
Output
Direction
Specify the number format you want to use for the bus.
Select the number of data input bits to the left of the binary point, including
the sign bit.
Select the number of data input bits to the right of the binary point. This
option applies only to signed fractional formats.
Preliminary
Complex input.
Real part output.
Imaginary part output.
(Note 1)
VHDL
Description
Description
DSP Builder Standard Blockset Libraries
Type
Implicit
3–13
(4)