IPT-DSPBUILDER Altera, IPT-DSPBUILDER Datasheet - Page 141

• Manufacturer Part Number: IPT-DSPBUILDER
• Description: DSP BUILDER SOFTWARE
• Manufacturer: Altera
• Type: DSPr

Specifications of IPT-DSPBUILDER

• Function: DSP Builder
• License: Initial License
• Software Application: IP CORE, DSP BUILDER
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: Not applicable / Not applicable

Chapter 8: Using Black Boxes for HDL Subsystems
Subsystem Builder Design Example
Simulating the Subsystem Builder Model
Adding VHDL Dependencies to the Quartus II Project and ModelSim
© June 2010 Altera Corporation
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To run the Simulink simulation, follow these steps:
1. Click Start on the Simulation menu in the filter8tap.mdl window to begin the
2. Double-click the Scope block to view the simulation results. Click Autoscale to
3. Click the Zoom X-axis icon and use the cursor to zoom in on the first 22 x-axis time
Figure 8–9. Simulink Simulation Results of 8-Tap FIR Filter, Scope Window
Because the input is a pulse, the simulation results show the impulse response of the
8-tap FIR filter, which translates to the eight coefficient values. You can change the
input stimulus to verify the step and random response of the filter.
The VHDL file is dependent on two other VHDL files. The Quartus II software or
ModelSim do not examine these two files, and compilation either fails or gives
unexpected results. To resolve this issue, follow these steps:
1. Double-click on the Signal Compiler block and click Compile. Ignore the
2. Copy the extra_add.tcl and extra_add_msim.tcl files from the original design
The extra_add.tcl file adds final_add.vhd and four_mult_add.vhd to the Quartus II
project, while extra_add_msim.tcl compiles them in ModelSim when your design is
run using the TestBench block. The Quartus II software executes any files ending
with _add.tcl when it creates the project. ModelSim executes files ending with
_add_msim.tcl when it compiles your design testbench.
simulation.
resize the scope.
units.
Figure 8–9
result for now. This action creates a DSPBuilder_filter8tap_import directory in
the directory containing your design.
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directory to the DSPBuilder_filter8tap_import directory.
Alternatively, you can create the directory DSPBuilder_filter8tap_import
directly.
shows the simulation results.
Preliminary
DSP Builder Standard Blockset User Guide
8–11